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TECHNICAL
DATA
SHEET
INT5130
Integrated Powerline MAC/PHY Transceiver Features
Single-chip powerline networking controller with IEEE802.3u MII interface Implements Intellon's PowerPacketTM technology which is fully compliant with the HomePlug Powerline Alliance Industry Specification v1.0 General purpose 8-wire serial PHY data interface Selectable MDI/SPI PHY management interface Up to 14 Mbps data rate on the powerline Orthogonal Frequency Division Multiplexing (OFDM) with patented signal processing techniques for high data reliability in noisy media conditions Intelligent channel adaptation maximizes throughput under harsh channel conditions Integrated quality-of-service (QoS) features such as prioritized random access, contention-free access, and segment bursting 56-bit DES Link Encryption with key management for secure powerline communications E2PROM interface for fast access to configuration parameters allows system designs to leverage standard Ethernet drivers IEEE 1149.1 JTAG Test Access Port 3.3 V signaling, 5 V tolerant interface Support for three status LEDs 144-pin LQFP package

Applications
Shared broadband Internet access using standard in-home powerlines Internet Appliances PC file and application sharing Peripheral and printer sharing Networked gaming

General Description
The INT5130 IC is an integrated powerline MAC/PHY transceiver providing No New WiresTM communications to any room, over any wire, at speeds of up to 14 Mbps. The INT5130 provides the ability to select between a complete Media Independent Interface (MII) or a reduced General Purpose Serial Interface (GPSI) for interconnection to the external MAC controller. The INT5130 also provides the option of selecting between a Management Data Interface (MDI) or a simple Serial Peripheral Interface (SPI) for handling the management and control of the MII/GPSI interface.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
The INT5130 implements Intellon's patented PowerPacket OFDM technology and is fully compliant with the HomePlug Powerline Alliance Industry Specification v1.0. Specifically tailored to reliably deliver up to 14 Mbps over the difficult powerline communication environment, the INT5130 combats deep attenuation notches, noises sources, and multi-path fading by allocating usable frequencies according to the signal to noise ratio (SNR). Synchronization is achieved in low SNR channels without the use of pilot carriers. The MAC implements a CSMA/CA scheme with prioritization and automatic repeat request (ARQ) for reliable delivery of Ethernet packets via packet encapsulation. Built-in quality-of-service (QoS) features provide the necessary bandwidth for multimedia payloads including voice, data, audio, and video. Prioritized random access along with segment bursting minimizes the demands on the receiver resources and maximizes the throughput of the network while still providing excellent latency response and jitter performance. The INT5130's contention-free access capability extends this concept of segment bursting to allow the transmission of multiple frames over the powerline without relinquishing the control of the medium. Utilizing contention-free access, a single station may act as a controller for the entire network. System designers have the option of embedding PowerPacket-specific control information within the packet stream for optimal control and performance or may choose to provide this information via the separate E2PROM interface. Providing this configuration and control information through a separate E2PROM interface allows the system designer to leverage standard Ethernet drivers. The INT5130 operates on both 2.5V and 3.3V supplies, offers 5V I/O tolerance, and is packaged in a 144-pin LQFP. Intellon offers a complete solution for powerline communication applications by providing the INT5130 in conjunction with the INT1000 Analog Conversion IC.
Functional Block Diagram
INT5130
RESET
PowerPacket MAC Interface Block PowerPacket PHY
ROM Config Regs RISC uProc Core PHY Core AFE Interface RAM
Power & GND
MDIO Control MDCLK/MDIO - OR SPI Control SDI,SDO,SCLK,CS MDI/SPI Select MII RX[3:0],RXCLK,RXDV,RX_ER TX[3:0],TXCLK,TXEN,TX_ER COL,CRS - OR GPSI RXD,RXCLK,RXEN TXD,TXCLK,TXEN COL,TXBSY MII/GPSI Select
Gain Control
MII/GPSI Interface
Arbiter
DMA & Link Sequencer
ADC DAC IFace
Buffer RAM JTAG Port
JTAG Control
MDIO Address Select
Configuration EEPROM Control
E2PROM Control
LED Control
LEDs
CLK IN
CLK OUT
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Contents
Features .......................................................................................................................................................... 1 Applications.................................................................................................................................................... 1 General Description........................................................................................................................................ 1 Functional Block Diagram.............................................................................................................................. 2 Contents ......................................................................................................................................................... 3 Pin I/O.............................................................................................................................................................. 4 Pin Descriptions by Group............................................................................................................................. 5 Pin Diagram .................................................................................................................................................... 9 Functional Description................................................................................................................................. 10 MII Data Interface with MDI Control .......................................................................................................... 11 MII Interface............................................................................................................................................ 11 MDI Control Interface............................................................................................................................. 17 MII Management Register Set ............................................................................................................... 18 GPSI Interface with SPI Control................................................................................................................ 21 GPSI Interface........................................................................................................................................ 21 SPI Slave Interface ................................................................................................................................ 24 Clocks........................................................................................................................................................ 25 AFE Interface............................................................................................................................................. 26 ADC/DAC Interface ................................................................................................................................ 26 AGC Circuitry......................................................................................................................................... 29 SPI Master Interface.................................................................................................................................. 29 SPI Master Timing Diagram................................................................................................................... 30 SPI Master DC Characteristics.............................................................................................................. 30 LEDs .......................................................................................................................................................... 30 JTAG Port.................................................................................................................................................. 31 JTAG Timing Diagrams ......................................................................................................................... 31 JTAG DC Characteristics ...................................................................................................................... 32 Application Diagrams................................................................................................................................... 34 Electrical Specifications............................................................................................................................... 35 Recommended Operating Conditions......................................................................................................... 35 DC Characteristics ....................................................................................................................................... 35 Physical Dimensions.................................................................................................................................... 36 Ordering Information.................................................................................................................................... 37
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Pin I/O
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Signal VDD_C VDD_C VDD_IO MII_TX3 VSS_C MII_TX2 VDD_C MII_TX1 VSS_IO VSS_C MII_TX0/ GPSI_TXD MII_TXEN/ GPSI_TXEN VDD_C MII_TXCLK/ GPSI_TXCLK VDD_Q MII_TX_ER VDD_C MII_RX_ER/ GPSI_RXD VSS_C VSS_C VSS_Q MII_RXCLK/ GPSI_RXCLK VDD_C VDD_C MII_RXDV/GPSI_ TXBSY VSS_C MII_RX3 VDD_C MII_RX2 VSS_C MII_RX1 VDD_C MII_RX0 VSS_C VSS_IO VSS_C Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Signal VDD_C VDD_C VDD_IO MII_COL/ GPSI_COL VSS_C MII_CRS/ GPSI_RXEN VDD_C RESET_N VSS_IO VSS_C VSS_C CLKOUT CLKIN VDD_C VDD_Q SPI_CS VDD_C SPI_CLK VSS_C VSS_C SPI_DI VSS_C SPI_DO VDD_C LED0_N VSS_C LED1_N VDD_IO LED2_N VSS_C ADC_CAL VDD_C AGCENC_N VSS_IO ADC_CLK VSS_C Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Signal VDD_C DAC_CLK VSS_C TX_EN RX_EN VDD_C VDD_IO ADIO0 ADIO1 ADIO2 VSS_IO ADIO3 VSS_C ADIO4 ADIO5 VSS_C VSS_Q ADIO6 VDD_Q ADIO7 ADIO8 ADIO9 VDD_IO AGC0 AGC1 AGC2 VDD_C AGC3 VSS_C AGC4 AGC5 VDD_C AGC6 AGC7 VSS_IO VSS_C Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Signal VDD_C VDD_IO TEST1 TEST2 VSS_C TCK VDD_C TDO VSS_C VSS_C VSS_C TDI VDD_C VDD_C VDD_C TMS VDD_C MDI_SPIS_N VSS_C VSS_C TRST_N VSS_Q NC VDD_C MII_MDCLK/ SPIS_SCLK VSS_C MII_MDIO/ SPIS_SDO VDD_IO MDI_ADRSEL[1]/SPIS _SDI VSS_C MDI_ADRSEL[0]/SPIS _CS_N VDD_C MII_GPSI_N VSS_IO VSS_C VSS_C
Table 1: Pin I/O
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Pin Descriptions by Group
Signal Name I/O Pad Description Signal Description
Media Independent Interface (MII)
These pins are multiplexed with the GPSI pins and are selected when MII_GSPI_N signal is at VDD.
MII_RX[3:0]
Output
MII_RXCLK
Output
MII_RXDV
Output
MII_RX_ER
Output
MII_TX[3:0]
Input
MII_TXCLK
Output
MII_TXEN
Input
MII_TX_ER
Input
MII_CRS
Output
MII_COL
Output
MII Receive Data. Data is transferred from the INT5130 to the external MAC across these four lines one nibble at a time. MII Receive Clock The receive clock outputs a continuous 25MHz clock to the external MAC. MII Receive Data Valid This signal indicates that the incoming data on the MII_RX[3:0] pins are valid. MII Receive Error This signal indicates to the external MAC that an error has occurred during the frame reception. MII Transmit Data Data is transferred to the INT5130 from the external MAC across these four lines one nibble at a time. MII Transmit Clock The transmit clock outputs a continuous 25MHz clock to the external MAC. MII Transmit Enable This signal indicates to the INT5130 that valid data is present on the MII_TX[3:0] pins. MII Transmit Error MII_TX_ER is activated by the external host controller when an error condition is detected during packet transmission. The INT5130 will ignore any MII transmission within which MII_TX_ER is asserted. MII_TX_ER is ignored if MII_TXEN is not asserted. MII Carrier Sense This signal indicates to the external host that traffic is present on the powerline and the host should wait until the signal goes invalid before sending additional data. This signal is an asynchronous output signal. MII Collision Detect This signal indicates to the external host that a collision has occurred on the MII interface. This signal is an asynchronous output signal.
MII Management Data Interface (MDI)
These pins are multiplexed with the SPIS_SDO and SPIS_SCLK signals and are selected when MDI_SPIS_N is at VDD.
MII_MDIO
Input/Output
MII_MDCLK
Input
MII Management Data Input/Output This bi-directional signal carries the data for the Management Data Interface. MII Management Data Clock Clock reference for the MII_MDIO signal.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
General Purpose Serial Interface (GPSI)
These pins are multiplexed with the MII pins and are selected when MII_GSPI_N signal is at VSS.
GPSI_RXD
Output
GPSI_RXCLK
Output
GPSI_TXD
Input
GPSI_TXCLK
Output
GPSI_RXEN GPSI_TXEN
Output Input
GPSI_TXBSY
Output
GPSI_COL SPI Slave Port
Output
GPSI Receive Data This signal carries data received from the powerline and delivers to the external host. Data is driven on the falling edge of the GPSI_RXCLK. GPSI Receive Clock This signal is the timing reference for the serial data transfer from the INT5130 to the external host. This clock operates at 10 MHz. GPSI Transmit Data This signal carries data transmitted from the external host to the INT5130 for transmission over the powerline. Data is latched on the falling edge of the GPSI_TXCLK. GPSI Transmit Clock This signal is the timing reference for the serial data transfer from the external host to the INT5130. This clock operates at 10 MHz. GPSI Receive Enable Indicates valid data is on the GPSI_RXD line. GPSI Transmit Enable Indicates when the external host is providing valid data on GPSI_TXD. GPSI Transmit Busy The GPSI Transmit Busy signal is asserted within 120 GPSI clocks after GPSI_TXEN indicates a TX frame is being sent by the local host. GPSI_TXBSY stays true until the entire TX frame is loaded into an internal buffer AND a new buffer is allocated to the GPSI TX interface. This signal should be monitored by the GPSI TX host. A new GPSI TX frame should not be sent until GPSI_TXBSY returns to false to prevent TX buffer overflows. GPSI_TXBSY is an asynchronous output signal. GPSI Collision Detect This signal is driven false in GPSI mode.
Selected when MDI_SPIS_N signal is at VSS.
SPIS_SDO SPIS_SDI
Output Input
SPIS_SCLK SPIS_CS_N
Input Input
SPI Slave Data Out SPI data from the INT5130 to the external host. SPI Slave Data In SPI data from the external host to the INT5130. This pin is shared with the MDI_ADRSEL[1]. SPI Slave Clock Timing reference signal for SPI_SDI and SPI_SDO. SPI Slave Chip Select Enables SPI data transfers on the INT5130. This pin is shared with the MDI_ADRSEL[0].
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SPI Master Port (Configuration PROM Interface) SPI_DO Output SPI Master Data Out INT5130 configuration data from the INT5130 to the external E2PROM. SPI Master Data In INT5130 configuration data from the external E2PROM to the INT5130. SPI Master Clock Timing reference signal for SPI_DI and SPI_DO. SPI Master Chip Select Enables data transfers on the SPI Master Interface.
SPI_DI
Input
SPI_CLK SPI_CS LED Control LED0_N
Output Output
Output
LED1_N
Output
LED2_N
Output
LED0_N: Collision Detection Activate for a duration of 10 ms upon detection of a collision. LED1_N: Activity Detection Activate for a duration of 10 ms upon the receipt of a properly addressed unicast or broadcast frame or the transmission of a frame. LED2_N: Link Detection Turns on when initialization is complete successfully and "network" is established.
Analog Front End Interface ADC_CLK Output ADC Clock ADC clock output to the INT1000 Analog Conversion IC. DAC Clock DAC clock output to the INT1000 Analog Conversion IC. Analog Front End Transmit Enable Transmit Enable signal Analog Front End Receive Enable Receive Enable signal Analog/Digital I/O ADC and DAC Data. Multiplexed parallel interface to INT1000 Analog Conversion IC. AGC Gain Select Gain control driven by the INT5130 to set the AGC level. ADC Calibrate This pin must remain low during normal operation of the ADC. It is pulsed high to request a calibration cycle. The ADC_CAL minimum pulse width is 4 clock cycles. While this signal is high the ADC calibration registers are cleared and the calibration control circuitry is reset. The ADC_CAL pulse will go high 217 clock cycles (2.6 ms) after power on reset drops, and will remain high for the required 4 clock cycles. 7 ADVANCE INFORMATION
DAC_CLK
Output
TX_EN RX_EN ADIO[9:0]
Output Output Input/Output
AGC[7:0]
Output
ADC_CAL
Output
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
AGCENC_N
Input
AGC Encode An inactive signal (logic 1) applied to this input selects unitary AGC format. An active signal (logic 0) applied to this input selects encoded AGC format
Test Access Port TCK TDI TMS TDO TRST_N Input Input Input Output Input Test Clock Test Clock for the IEEE 1149.1 JTAG Port Test Data In Data In for the IEEE 1149.1 JTAG Port Test Mode Select Test Mode Select for the IEEE 1149.1 JTAG Port Test Data Out Data Out for the IEEE 1149.1 JTAG Port Test Reset This pin will be used to reset the TAP controller. It should be connected to ground when the JTAG port is not in use.
System Control RESET_N Input Reset Resets logic circuitry, but not clock circuitry. Reset is active low and should be held low for a minimum of 100 ns. Clock Input 100 MHz clock input. Driven by an external oscillator or an external crystal (feedback path for crystal implementation provided by CLKOUT) Note: CLKIN connects directly to the 2.5 V core of the IC and does not connect to the 3.3 V I/O ring. Therefore, this pin is not 3.3 or 5 V tolerant. Clock Output 100 MHz clock feedback path when a crystal is implemented. This pin should be left as NO CONNECT if an external oscillator is implemented on CLKIN. Note: CLKOUT connects directly to the 2.5 V core of the IC and does not connect to the 3.3 V I/O ring. Therefore, this pin is not 3.3 or 5 V tolerant. MDI PHY Address Selection Address select used to compare against the upper two bits of the MDI Address. These pins share function with SPIS_CS_N and SPIS_SDI and should be pulled-up or down with external resistors to set the appropriate value which is read by the INT5130 during power up. Management Data Interface/Serial Peripheral Interface Slave Select. Selects which PHY management signals are active. Media Independent Interface/General Purpose Serial Interface Select. Selects which PHY data interface signals are active.
CLKIN
Clock Pad
CLKOUT
Clock Pad
MDI_ADRSEL[1:0]
Input
MDI_SPIS_N
Input
MII_GPSI_N
Input
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
TEST1 TEST2 NC Power Supplies VDD_C VSS_C VDD_IO VSS_IO VDD_Q VSS_Q
Input Input ---
Factory Test Pin 1 Tie to I/O Ground Factory Test Pin 2 Tie to I/O Ground No Connect
2.5v 3.3v 3.3v
Digital Power Digital Ground I/O Power I/O Ground Quiet Power Connect to I/O Power Quiet Ground Connect to I/O Ground Table 2: Pin Descriptions by Group
Pin Diagram
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VSS_C VSS_C VSS_IO MII_GPSI_N VDD_C MDI_ADRSEL[0]/SPIS_CS_N VSS_C MDI_ADRSEL[1]/SPIS_SDI VDD_IO MII_MDIO/SPIS_SDO VSS_C MII_MDCLK/SPIS_SCLK VDD_C NC VSS_Q TRST_N VSS_C VSS_C MDI_SPIS_N VDD_C TMS VDD_C VDD_C VDD_C TDI VSS_C VSS_C VSS_C TDO VDD_C TCK VSS_C TEST2 TEST1 VDD_IO VDD_C
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_C VDD_C VDD_IO MII_COL/GPSI_COL VSS_C MII_CRS/GPSI_RXEN VDD_C RESET_N VSS_IO VSS_C VSS_C CLKOUT CLKIN VDD_C VDD_Q SPI_CS VDD_C SPI_SCLK VSS_C VSS_C SPI_DI VSS_C SPI_DO VDD_C LED0_N VSS_C LED1_N VDD_IO LED2_N VSS_C ADC_CAL VDD_C AGCENC_N VSS_IO ADC_CLK VSS_C
VDD_C VDD_C VDD_IO MII_TX3 VSS_C MII_TX2 VDD_C MII_TX1 VSS_IO VSS_C MII_TX0/GPSI_TXD MII_TXEN/GPSI_TXEN VDD_C MII_TXCLK/GPSI_TXCLK VDD_Q MII_TX_ER VDD_C MII_RX_ER/GPSI_RXD VSS_C VSS_C VSS_Q MII_RXCLK/GPSI_RXCLK VDD_C VDD_C MII_RXDV/GPSI_TXBSY VSS_C MII_RX3 VDD_C MII_RX2 VSS_C MII_RX1 VDD_C MII_RX0 VSS_C VSS_IO VSS_C
INT5130
VSS_C VSS_IO AGC7 AGC6 VDD_C AGC5 AGC4 VSS_C AGC3 VDD_C AGC2 AGC1 AGC0 VDD_IO ADIO9 ADIO8 ADIO7 VDD_Q ADIO6 VSS_Q VSS_C ADIO5 ADIO4 VSS_C ADIO3 VSS_IO ADIO2 ADIO1 ADIO0 VDD_IO VDD_C RX_EN TX_EN VSS_C DAC_CLK VDD_C
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Functional Description
The interfaces that provide data, status, and control to and from the INT5130 include... * * * * * * External host interface provided via the Media Independent Interface (MII) format (described by IEEE802.3u, Clause 22) or a General Purpose Serial Interface (GPSI). Management control provided via the Management Data Interface (MDI) or the Serial Peripheral Interface (SPI). Analog Front End interface. LEDs indicating network status. Optional E2PROM interface providing a path to initialize the INT5130 with PowerPacket-specific configuration information. The JTAG port implements the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
LEDS
ROM MDI or SPI
RAM
Config Regs
RISC uProcessor Core
Link Sequencer
PHY Seq PHY Core
ADIO(9:0) AFE Logic AGC(7:0)
MII or GPSI
MII/GPSII Interface
Interface DMA
Arbiter
PHY DMA
FIFOs
TEST
JTAG
Buffer RAM
E2PROM
SPI Master Interface Block
PowerPacket MAC
PowerPacket PHY
Figure 1: INT5130 Block Diagram
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
MII Data Interface with MDI Control
Data communication between the INT5130 and the external host controller is provided via the Media Independent Interface or a reduced General Purpose Serial Interface. The MII_GPSI_N select pin is included on the chip interface to configure the INT5130 in either MII mode or GPSI mode. Access to the INT5130's internal MII status and control registers is via the Management Data Interface or a SPI interface. The MDI_SPIS_N select pin is included on the chip interface to configure the INT5130 in either MDI mode or SPI mode. The information that follows describes the MII communication interface along with the MDI management interface as a typical example.
INT5130
MII_RX(3:0) MII_RXCLK MII_RX_ER MII_RXDV MII_CRS
PowerPacket MAC
MII_COL
Interface Block
External Host Controller
MII_TX(3:0) MII_TXCLK MII_TX_ER MII_TXEN
MII_MDCLK MII_MDIO
Figure 2: MII Data Interface with MDI Control
MII Interface
MII is an industry standard, multi-vendor, interoperable interface between separate MAC and PHY devices. It provides a simple interconnection between the INT5130 and IEEE802.3 Ethernet MAC controllers (commonly referred to as external host controllers in this document) available from a variety of IC suppliers. The MII consists of separate 4-bit data paths for transmit and receive data along with carrier sense and collision detection. Data is transferred between the MAC and PHY over each 4-bit data path synchronous with a clock signal supplied to the host by the INT5130. The MII interface also provides a two wire bidirectional serial management data interface (MDI). This interface provides access to the status and control registers in the INT5130.
MII Timing Diagrams
Figure 3 below shows the transmission behavior of the MII interface. Figure 4 shows the receive behavior of the MII interface. Figure 5 shows an unsuccessful attempt to transmit a packet, resulting in a collision. NOTE: MII_CRS is asynchronous to MII_TXCLK.
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PowerPacket PHY
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
MII_TXCLK
MII_CRS
MII_TXEN
MII_TXD[3:1], MII_TX0
DATA
DATA
DATA
DATA
MII_COL
Figure 3: MII TX Waveform
MII_RXCLK
MII_CRS
MII_RXDV
MII_RXD[3:0]
DATA
DATA
DATA
DATA
Figure 4: MII RX Waveform
MII_CRS
MII_TXEN
MII_RXDV
MII_COL
Figure 5: MII TX With Collision Based On RX Activity
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MII_RXCLK
tMII_RVAL
MII_RXD[3:0], MII_RXDV, MII_RX_ER, MII_COL, MII_CRS
DATA
Figure 6: MII Receive Timing Diagram
MII_TXCLK
tMII_TSU
MII_TXD[3:1], MII_TX0, MII_TXEN, MII_TX_ER
DATA
tMII_TH
Figure 7: MII Transmit Timing Diagram
MII DC Characteristics
Parameter Symbol Receive Timing tMII_RVAL MII_RX[3:0], MII_RXDV valid from MII_RXCLK measured from Vilmax = 0.8V or measured from Vihmin = 2.0V 0 25 ns
Parameter Name
Test Condition
Min
Max
Unit
Transmit Timing MII_TXEN, MII_TX0, MII_TX[3:1] measured from Vilmax = 0.8V or setup to MII_TXCLK measured from Vihmin = 2.0V
tMII_TSU
8
ns
tMII_TH
MII_TXEN, MII_TX0, MII_TX[3:1] measured from Vilmax = 0.8V or hold to MII_TXCLK measured from Vihmin = 2.0V
0
ns
Table 3: MII DC Characteristics
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MII Signal Descriptions
The following description references Clause 22, Media Independent Interface specification, used in the 100 Mbps half-duplex mode. The MII is used as a data channel that transfers data back and forth with flow controlled by the carrier sense signal (MII_CRS). MII_TXCLK and MII_RXCLK The INT5130 generates a stable, continuous 25 MHz square wave that is supplied on MII_TXCLK and MII_RXCLK. These clocks provide the timing reference for the transfer of the MII_TXEN and MII_TX signals, as well as MII_RX, MII_RX_ER, and MII_RXDV. MII_RX_ER MII_RX_ER is activated when the INT5130 detects an error in the receive stream as a result of decoding. MII_TX_ER MII_TX_ER is activated by the external host controller when an error condition is detected during packet transmission. The INT5130 will ignore any MII transmission within which MII_TX_ER is asserted. MII_TX_ER is ignored if MII_TXEN is not asserted. MII_TXEN MII_TXEN from the external host provides the framing for the Ethernet packet. An active MII_TXEN indicates to the INT5130 that data on MII_TX[3:0] should be sampled using MII_TXCLK. MII_TX[3:0] MII_TX[3:0] contains the data to be transmitted and transitions synchronously with respect to MII_TXCLK. MII_TX[0] is the least significant bit. It is generally assumed that the data will contain a properly formatted Ethernet frame. That is, the first bits on MII_TX[3:0] correspond to the preamble, followed by SFD and the rest of the Ethernet frame (DA, SA, length/type, data, CRC). MII_RXDV MII_RXDV is asserted by the INT5130 to indicate that the INT5130 has decoded receive data to present to the external host. MII_RX[3:0] MII_RX[3:0] contains the data recovered from the medium by the INT5130 and transitions synchronously with respect to MII_RXCLK. MII_RX[0] is the least-significant bit. The INT5130 formats the frame such that the external MAC will be presented with expected preamble plus SFD. MII_CRS MII_CRS is used to tell the external host when the INT5130 is available for sending a packet. MII_CRS is asynchronous to MII_TXCLK. When a packet is being transmitted, CRS is held high. CRS will go low whenever the INT5130 is ready to accept another packet. On transmit, the INT5130 asserts MII_CRS some time after MII_TXEN becomes active, and drops MII_CRS after MII_TXEN goes inactive AND when the INT5130 is ready to receive another packet from the external host for transmission. When MII_CRS has been negated for at least 900ns, the external MAC may assert MII_TXEN again if there is another packet to send. This differs from nominal behavior of MII_CRS in that MII_CRS can extend past the end of the packet by an
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
arbitrary amount of time, while the INT5130 is gaining access to the channel and transmitting the packet. MII_CRS does not affect the receive side of the channel. Once packets start arriving from the powerline medium and begin transmission to the external host controller over the MII interface, the external host MUST be ready to receive or the packet can be lost. Note that external MACs programmed to run in 100 Mbps mode do not use a jabber timeout, so there is no timing restriction on how long MII_CRS can be asserted.
320 ns (32 Bit times) 320 ns (32 Bit times) 320 ns (32 Bit times) 320 ns (32 Bit times)
MII_CRS MII_TXEN MII_TX[3:1], MII_TX0
Internal TX buffer available pulse P P
MII_RX[3:0] MII_RXDV
Internal RX buffer available pulse
P
P
P
MII_COL
Case 1
TX only
Case 2
RX Only
Case 3
RX while TX, delayed TX buffer avail
Case 4
RX while no TX buf avail
Case 5
TX Buf avail
Figure 8: MII Flow Control Overview Part 1
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
MII_CRS
MII_TXEN
MII_TX[3:1], MII_TX0
P
P
P
MII_RX[3:0]
P
MII_RXDV
MII_COL Case 6 Case 7 TX only TX overrun Frame dropped Case 8 Collision
Figure 9: MII Flow Control Overview Part 2
MII Frame Structure
The frame structure transmitted on the MII or GPSI interface is the following sequence of fields:
Interframe Gap
Preamble
Start Frame Delimiter
Data
Interframe Gap A period on the MII interface during which no data activity occurs on the MII. Preamble Begins a frame transmission that consists of 7 octets with the following bit values... 10101010 10101010 10101010 10101010 10101010 10101010 10101010 The preamble is stripped by the INT5130 when transmitting (the preamble is not transmitted on the PLC medium) and pre-pended by the INT5130 when receiving. Start Frame Delimiter Indicates the start of a frame and follows the preamble. The SFD bit sequence is 10101011. The start frame delimiter is stripped by the INT5130 when transmitting (the SFD is not transmitted on the PLC medium) and pre-pended by the INT5130 when receiving.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Data Data sent over the MII interface consists of N bytes of data transmitted as 2N nibbles.
The de-assertion of the MII_TXEN signals the End Of Frame (EOF) for data transmitted on the MII_TX[3:0] pins. Likewise, the de-assertion of the MII_RXDV signals the EOF for data transmitted on MII_RX[3:0].
MACs Serial Bit Stream LSB First nibble LSB D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 MSB Second nibble
MII Nibble Stream
MSB
Figure 10: Partition of Serial Bit Stream to Nibble Stream
MDI Control Interface
The Management Data Interface connects the external host to the INT5130 for purposes of controlling the INT5130 and gathering status. A specific frame format and protocol definition exists for exchanging management frames over this interface. A register definition exists as well that specifies a basic register set with an extension mechanism. The INT5130 implements the basic register set only.
MDI Timing Diagrams
MII_MDCLK
tMDI_RVAL
MII_MDIO
Figure 11: MDI Receive Timing Diagram
DATA
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
MII_MDCLK
tMDI_TSU
MII_MDIO
DATA
tMDI_TH
Figure 12: MDI Transmit Timing Diagram
MDI DC Characteristics
Parameter Symbol Receive Timing tMDI_RVAL MII_MDIO valid from MII_MDCLK measured from Vilmax = 0.8V or measured from Vihmin = 2.0V 0 300 ns Parameter Name Test Condition Min Max Unit
Transmit Timing tMDI_TSU MII_MDIO setup to MII_MDCLK measured from Vilmax = 0.8V or measured from Vihmin = 2.0V
10
ns
tMDI_TH
MII_MDIO hold to MII_MDCLK
measured from Vilmax = 0.8V or measured from Vihmin = 2.0V
10
ns
Table 4: MDI DC Characteristics
MDI Signal Descriptions
Management Data Input/Output MII_MDIO is a bi-directional signal that is used to transfer status and control information between the INT5130 and the external host. Control information is driven by the external host synchronously with respect to MII_MDCLK and is sampled synchronously by the INT5130. Status information is transferred from the INT5130 to the external host in the same manner. Management Data Clock MII_MDCLK is sourced by the external host as the timing reference for transfer of information on the MII_MDIO signal.
MII Management Register Set
The IEEE 802.3u mandated management data registers for control and status are accessible via the Management Data Interface (MDI). These registers are also accessible via the industry supported serial peripheral interface. The MDI Port will only respond to addresses 0xbXX000 when the XX field (MSBits of the MDI address) match the state of the MDI_ADRSEL[1:0] input signals. These registers can also be
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
accessed from the SPI Slave port when the MDI_SPIS_N select line has been tied low to select the SPI Slave port.
PLCSR 0 1
Register Name Control Register Status Register
MII Mandated X X
Table 5: Powerline Control and Status Register (PLCSR) Summary
PRE READ WRITE 1...1 1...1
ST 01 01
OP 10 01
PHYAD AAAAA AAAAA
REGAD RRRRR RRRRR
TA Z0 10
Data DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD
Idle Z Z
Figure 13: MDI Frame Structure PRE (Preamble) At the beginning of each MDI transaction, the external host shall send a sequence of 32 contiguous logic "1" bits on the MDIO signal so the INT5130 can establish synchronization. The INT5130 needs to observe this 32 bit sequence on the MII_MDIO signal before it responds to any transaction. ST (Start of Frame) Indicated by a "01" pattern. OP (Operation Code) "10" indicates a READ. "01" indicates a WRITE. PHYAD (PHY Address) The PHY Address is 5 bits, allowing up the 32 unique PHY addresses. The INT5130 will respond to PHY addresses indicated by 0bXX000. The "XX" bits of the PHY address are controlled by the INT5130 interface pins MDI_ADRSEL(0:1). This allows the designer to assign the INT5130 to one of 4 unique PHY addresses. REGAD (Register Address) The Register Address is 5 bits and is used to index the maximum of 32 individual registers in the MDI address space. The INT5130 only implements the two mandated MII registers. 0b00000 will index the MII Control Register and 0b00001 will index the MII Status Register. TA (Turnaround) The turnaround time is a 2 bit time spacing between the Register Address field and the Data field to avoid contention during a read transaction. For reads, both the external host and the INT5130 will remain in tri-state for the first bit time. The INT5130 will drive a "0" during the second bit time.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
For writes, the external host will drive a "1" for the first bit time and a "0" bit for the second bit time. Data The data field is 16 bits. The first data bit transmitted and received shall be bit 15 of the register being addressed.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
GPSI Interface with SPI Control
The General Purpose Serial Interface (GPSI) is a flexible, bi-directional serial interface that can be utilized in place of the MII. It provides a straightforward interface to a communications controller through a synchronous serial data stream for transmit and receive data. When using the GPSI interface, the management interface can either be MDI or SPI, selected by the MDI_SPIS_N pin. The information that follows describes the GPSI communication interface along with the SPI management interface as a typical example.
GPSI_RXD GPSI_RXCLK GPSI_RXEN GPSI_COL GPSI_TXBSY GPSI_TXD
INT5130
GPSI_TXEN
SPIS_SDO SPIS_SDI SPIS_SCLK SPIS_CS_N
Figure 14: GPSI Data Interface with SPI Control
GPSI Interface
GPSI is an interoperable interface providing a simple interconnection between the INT5130 and embedded microcontrollers. Data is transferred between the host controller and the INT5130 over separate 1-bit transmit and receive data paths synchronous with clock signals supplied to the host by the INT5130.
GPSI Timing Diagrams
The figures below show the transmission and reception of packets and the corresponding behavior of the GPSI interface. A packet is transferred from the host when GPSI_TXEN goes high. An unsuccessful attempt is made to transmit a packet in Case 5. The received packet is passed to the host when GPSI_RXEN is high.
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PowerPacket PHY
Interface Block
External Host Controller
PowerPacket MAC
GPSI_TXCLK
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
GPSI_TXEN
GPSI_TXD
P
P
P
P
GPSI_TXBSY
Internal TX buffer available pulse
GPSI_RXEN
GPSI_RXD
P
P
Internal RX buffer available pulse
GPSI_COL Case 1
TX only
Case 2
RX Only
Case 3
RX & TX
Case 4
TX, buf avail
Case 5
TX, No buf avail, Frame dropped
Figure 15: GPSI Flow Control Diagram
tGPSI_TPER GPSI_TXCLK
tGPSI_THIGH
tGPSI_TDELAY GPSI_TXD
t GPSI_TDELAY
GPSI_TXEN tGPSI_TTXBSYH GPSI_TXBSY
GPSI_COL
Figure 16: GPSI Transmit Timing Diagram
t GPSI_RPER GPSI_RXCLK t GPSI_RSU GPSI_RXD t GPSI_RDH GPSI_RXEN
t GPSI_RHIGH tGPSI_RLOW
t GPSI_RRXENH
GPSI_COL
Figure 17: GPSI Receive Timing Diagram
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
GPSI DC Characteristics
Parameter Symbol
Parameter Name
Test Condition @ 1.5 V @ 1.5 V @ 1.5 V
Min 99.99 40 40 15
Max 100.01 60 60
Unit ns ns ns ns
Receive Timing tGPSI_RPER GPSI_RXCLK Period tGPSI_RHIGH GPSI_RXCLK High Time tGPSI_RLOW tGPSI_RSU GPSI_RXCLK Low Time
GPSI_RXD and GPSI_RXEN Setup to @ 1.5 V GPSI_RXCLK GPSI_RXD Hold after GPSI_RXCLK @ 1.5 V GPSI_RXEN Hold after GPSI_RXCLK @ 1.5 V
tGPSI_RDH tGPSI_RRXENH
15 0
ns ns
Transmit Timing tGPSI_TPER GPSI_TXCLK Period tGPSI_THIGH GPSI_TXCLK High Time tGPSI_TDELAY GPSI_TXD and GPSI_TXEN Delay from GPSI_TXCLK
@ 1.5 V @ 1.5 V @ 1.5 V
99.99 40 0
100.01 60 70
ns ns ns
tGPSI_TRXENH
GPSI_RXEN Hold after GPSI_TXEN @ 1.5 V
0
ns
Table 6: GPSI DC Characteristics
GPSI Signal Descriptions
GPSI_TXCLK and GPSI_RXCLK: The INT5130 generates a stable, continuous 10 MHz square wave that is supplied on GPSI_TXCLK and GPSI_RXCLK. These clocks provide the timing reference for the transfer of the GPSI_TXEN and GPSI_TXD signal, as well as GPSI_RXEN and GPSI_RXD. GPSI_RXD: GPSI_RXD contains the data recovered from the medium by the INT5130 and transitions synchronously with respect to GPSI_RXCLK. The INT5130 properly formats the frame such that the external host controller will be presented with the expected preamble plus SFD. GPSI_RXEN: GPSI_RXEN is asserted by the INT5130 to indicate that the INT5130 has decoded receive data to present to the external host controller. GPSI_TXBSY: GPSI_TXBSY is an optionally used signal to tell the external host controller when the INT5130 is available for sending packets. When a packet is being transmitted, GPSI_TXBSY is held high. GPSI_TXBSY will go low whenever the INT5130 is ready to send another packet. If this signal is not used, the transmitting logic must pace the packet transmissions to ensure that no packets are lost due to buffer overflow.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
On transmit, the INT5130 asserts GPSI_TXBSY some time after GPSI_TXEN becomes active, and drops GPSI_TXBSY after GPSI_TXEN goes inactive AND when the INT5130 is ready to accept another packet for transmission. When GPSI_TXBSY falls, the external host controller may assert GPSI_TXEN again if there is another packet to send. GPSI_TXBSY does not affect nor reflect the receive side of the channel. Once packets start arriving off of the powerline medium and begin transmission to the external host controller over the GPSI interface, the external host controller MUST be ready to receive or the packet can be lost. GPSI_TXEN: GPSI_TXEN from the external host provides the framing for the Ethernet packet. An active GPSI_TXEN indicates to the INT5130 that data on GPSI_TXD should be sampled using GPSI_TXCLK. GPSI_TXD: GPSI_TXD contains the data to be transmitted and transitions synchronously with respect to GPSI_TXCLK. It is generally assumed that the data will contain a properly formatted Ethernet frame (see MII Frame Structure above). That is, the first bits on GPSI_TXD correspond to the preamble, followed by Start Frame Delimiter (SFD) and the rest of the Ethernet frame (DA, SA, length/type, data, CRC).
SPI Slave Interface
The INT5130 implements a SPI Slave port that when connected to an external host controller containing a SPI Master, can be used to control access to the two configuration registers. The SPI Slave port uses a 16-bit control field (msb first) consisting of a 6-bit command field, a 5-bit reserved field, and a 5-bit address field to control access to the two configuration registers detailed above. Following the control field, the 16bit register contents are written or read based on the command field.
Register function 15 5 Write PLCSR0 (Control Register) Read PLCSR0 (Control Register) Write PLCSR1 (Status Register) Read PLCSR1 (Status Register) L L L L 14 13 12 11 Command Field 4 3 2 1 L L L L L L L L L L L L H H H H 10 0 L H L H
Control Field 8 7 6 5 Reserved Field 4 3 2 1 0 9 H H H H L L L L L L L L L L L L L L L L
4
3 2 1 Address Field 4 3 2 1 L L L L L L L L L L L L L L L L
0 0 L L H H
Table 7: SPI Slave Command Summary
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
SPI SlaveTiming Diagram
tSPIS_LOW tSPIS_HIGH
SPIS_SCLK SPIS_SDI
tSPIS_SU
MSB IN BITS 6-1 LSB IN
tSPIS_H
SPIS_SDO
MSB OUT
BITS 6-1
LSB OUT
t SPIS_SDOVD
tSPIS_CSLAG
SPIS_CS_N
tSPIS_CSLEAD
Figure 18: SPI Slave Signal Timing
SPI Slave DC Characteristics
Parameter Symbol tSPIS_F tSPIS_HIGH tSPIS_LOW tSPIS_SDOVD tSPIS_CSLEAD tSPIS_CSLAG tSPIS_SU tSPIS_H
Parameter Name SPIS_SCLK Frequency SPIS_SCLK High Time SPIS_SCLK Low Time SPIS_SDO Valid Output Delay from SPIS_SCLK SPIS_CS Lead to SPIS_SCLK SPIS_CS Lag from SPIS_SCLK SPIS_SDI Setup Time to SPIS_SCLK SPIS_SDI Hold Time to SPIS_SCLK
Test Condition @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V
Min 400 400 0 500 1500 200 200
Max 2.1
Unit MHz ns ns
500
ns ns ns ns ns
Table 8: SPI Slave DC Characteristics
Clocks
The INT5130 runs from a single 100MHz oscillator input and generates a 50MHz clock to feed the ADC, a 50MHz clock to feed the DAC, the 25MHz MII clock, and the 10MHz GPSI clock. The 100MHz clock input directly feeds the clock distribution network that clocks up to 60% of the digital logic. Note: Both CLKIN and CLKOUT connect directly to the 2.5 V core of the IC and do not connect to the 3.3 V I/O ring. Therefore these pins are not 3.3V or 5V tolerant. The oscillator must have 25 PPM RMS maximum tolerance including initial accuracy, temperature/voltage range and 5 years of aging. This oscillator must have a symmetry no worse than 40/60, jitter of 75 ps and 4 ns rise and fall time. The oscillator must be rated over the desired temperature range and 10% voltage range. The INT5130 uses a crystal input cell to receive the clock input.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
AFE Interface
The INT5130 provides a simple parallel interface to the analog front end (AFE). The analog data is clocked into or out of the INT5130 on a 10-bit bi-directional parallel data bus under control of transmit or receive enable signals and sample clock references provided to the AFE from the INT5130. The INT5130 also provides a parallel byte-wide automatic gain control interface.
ADIO[9:0]
TX_EN RX_EN ADC_CLK DAC_CLK ADC_CAL
INT1000 ADC / DAC IC
INT5130
AGC[7:0]
ADC_CAL
Pull-up or Pull-down
AGC Circuitry
Figure 19: AFE Interface to INT5130
ADC/DAC Interface
The INT5130 outputs a sequential stream of digital time samples of the OFDM waveforms for transmission. The digital transmit signal is passed on to the INT1000 Integrated Converter. The INT1000 consists of a 10-bit ADC and 10-bit DAC on a multiplexed 10-bit bi-directional data bus. The ADC digitizes the analog OFDM receive signal for input to the INT5130. The DAC converts digital samples into analog waveforms.
ADC/DAC Timing Diagrams
DAC_CLK
TX_EN
ADIO[9:0]
TX DATA
TX DATA
TX DATA
RX DATA
RX DATA
RX DATA
ADC_CLK
RX_EN
Figure 20: AFE TX and RX activity
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
tAFE_H
2.0V
DAC_CLK, ADC_CLK
1.5V 0.8V
tAFE_L
tAFE_R
tAFE_FT
tAFE_PW
Figure 21: AFE Clock Waveforms
DAC_CLK
tAFE_RVAL
ADIO[9:0], RX_EN, TX_EN
Figure 22: AFE Transmit Timing Diagram
DATA
ADC_CLK
tAFE_TSU
ADIO[9:0]
DATA
tAFE_TH
Figure 23: AFE Receive Timing Diagram
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
DAC DC Characteristics
Parameter Conditions Number of Bits Data Format Sample Rate DAC DATA OUTPUTS VOH HIGH level output voltage 1, 2 VOL LOW level output voltage 1, 3 TAFE_RVAL Propagation Delay Time 1 DAC CLOCK OUTPUT tAFE_PW DAC Clock Pulse Width 1 tAFE_R DAC Clock Rise Time 1 tAFE_FT DAC Clock Fall Time 1 tJ DAC Clock Jitter 1 Conditions: 1) VDD = 3.3V, CL = 15pF, RL = 1K 2) IOH = -1mA 3) IOL = 1mA Symbol Min Typical Max 10 Straight Binary Unit Bits MSPS V V ns ns ns ns ps rms
50 2.4 5.0 10 8.2 0.4 15.0 15 2 2 75
Table 9: DAC DC Characteristics
ADC DC Characteristics
Parameter Conditions Number of Bits Data Format Sample Rate ADC DATA INPUTS VIH HIGH level input voltage 1 VIL LOW level input voltage 1 TA Aperture Delay Time 1 tAFE_TSU Data Setup Time 1 tAFE_TH Data Hold Time 1 ADC CLOCK OUTPUT VOH HIGH level output voltage 1 VOL LOW level output voltage 1 tAFE_H ADC/DAC Clock Pulse Width 1 High tAFE_L ADC/DAC Clock Pulse Width 1 Low tAFE_R ADC/DAC Clock Rise Time 1 tAFE_FT ADC/DAC Clock Fall Time 1 tJ ADC/DAC Clock Jitter 1 Conditions: 1) VDD = 3.3V, CL = 15pF, RL = 1K Symbol Min Typical Max 10 Straight Binary Unit Bits MSPS V V ns ns ns V V ns ns ns ns ps rms
50 2.0 0.8 2.7 3 3 2.1 10 10 0.9 15 15 2 2 75
Table 10: ADC DC Characteristics
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
AGC Circuitry
The INT5130 receives 10-bit digitized samples from the INT1000 and uses them to adjust the Switched Gain Amplifier (SGA) gain to maintain optimum signal level at the input of the ADC. The AGC[7:0] control bus is used to pass a Gain Control Value (GCV) to the SGA. If the AGCENC_N input pin is low, the GCV is encoded on pins [3:0] of the AGC[7:0] control bus. If the AGCENC_N input pin is high, the GCV is decoded on pins [7:0] of the AGC[7:0] control bus with pins [7:4] selecting the gain switch setting for the first stage amplifier and pins [3:0] selecting the gain switch setting for the second stage amplifier.
GCV (AGCENC_N = 0) AGC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111
GCV (AGCENC_N = 1) AGC[7:4] AGC[3:0] 0000 0000 1000 1000 0100 1000 0010 1000 0001 1000 0001 0100 0001 0010 0001 0001
Front End Gain (dB) OFF 0 8 16 24 32 40 48
Note Mute RX during TX mode
Table 11: RX Gain Control Values
AGC DC Characteristics
Symbol Parameter Conditions VOH HIGH level output voltage 1 VOL LOW level output voltage 1 tR Rise time 1 tF Fall time 1 Conditions: 1) VDD = 3.3V, CL = 15pF, RL = 1K Min 2.1 Typical Max 0.9 5 5 Unit V V ns ns
Table 12: AGC IDC Characteristics
SPI Master Interface
The SPI Master interface gives the system designer the option of providing the INT5130 with the necessary configuration information from a simple, SPI-controlled E2PROM as opposed to supplying this information via PowerPacket MAC management frames (transmitted over the MII interface). The information stored in the E2PROM is intended to initialize the INT5130 with specific information that will not be changed throughout its normal course of operation. For specific features that require real-time control, such as those features found within the Set Transmit Characteristics MAC management frame, this information must be provided via the MAC management frames and not from the E2PROM. The E2PROM must be an Atmel AT93C46 programmed in 8-bit mode, or equivalent.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
SPI Master Timing Diagram
tSPI_HIGH tSPI_SU
SPI_SCLK
tSPI_LOW DATA tSPI_DIVD tSPI_CSVD
tSPI_H
SPI_DI
SPI_DO
DATA tSPI_CSL
SPI_CS
Figure 24: SPI Master Signal Timing Diagram
SPI Master DC Characteristics
Parameter Symbol tSPI_F tSPI_HIGH tSPI_LOW tSPI_DIVD tSPI_CSVD tSPI_CSL tSPI_SU tSPI_H Parameter Name SPI_SCLK Frequency SPI_SCLK High Time SPI_SCLK Low Time SPI_DI Valid Output Delay from SPI_SCLK SPI_CS Valid Output Delay from SPI_SCLK SPI_CS Low Time SPI_DO Setup Time to SPI_SCLK SPI_DO Hold Time to SPI_SCLK Test Condition @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V @ 1.5 V Min 70 70 0 0 1000 50 0 Max 6.125 90 90 15 15 Unit MHz ns ns ns ns ns ns ns
Table 13: SPI Master DC Characteristics
LEDs
Signal LED0_N Status Collision Description LED0_N: Collision Detection Activate for a duration of 250 ms upon detection of a collision. LED1_N: Activity Detection Activate for a duration of 250 ms upon the receipt of a properly addressed unicast or broadcast frame or the transmission of a frame. LED2_N: Link Detection Turns on when initialization is complete successfully and "network" is established. 30 ADVANCE INFORMATION
LED1_N
Activity
LED2_N
Link
INTELLON CONFIDENTIAL
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Table 14: LED Descriptions
JTAG Port
The JTAG port is implements the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
JTAG Timing Diagrams
tJTAG_H
2.0V
TCK
1.5V 0.8V
tJTAG_L
tJTAG_R
tJTAG_FT
tJTAG_P
Figure 25: JTAG (IEEE 1149.1) TCK Waveform
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
TCK TDI, TMS
tJTAG_SU
tJTAG_H tJTAG_VD
TDO
tJTAG_OVD tJTAG_OFD
Output Signals
tJTAG_ISU
Input Signals
tJTAG_IH
Figure 26: JTAG(IEEE 1149.1) Test Signal Timing
JTAG DC Characteristics
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Parameter Symbol tJTAG_F tJTAG_P tJTAG_H tJTAG_L tJTAG_R tJTAG_FT tJTAG_SU tJTAG_H tJTAG_VD tJTAG_FD tJTAG_OVD tJTAG_OFD tJTAG_ISU tJTAG_IH
Parameter Name TCK Frequency TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay All Inputs (Non-Test) Setup Time All Inputs (Non-Test) Hold Time
Test Condition
Min 100
Max 10
Unit MHz ns ns ns
@ 2.0V @ 0.8V
45 45 4 4 8 10 3 3 8 7 30 50 25 36
ns ns ns ns ns ns ns ns ns ns
Table 15: JTAG (IEEE 1149.1) DC Characteristics
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Application Diagrams
LEDs Powerline EEPROM LEDs AGC Amplifier 802.3 MAC Controller for PCI MII INT5130 Integrated Powerline MAC/PHY Transceiver
Coupler
PCI
MDI
INT1000 Analog Conversion IC
Line Driver
Figure 27: PCI to MII Application Diagram
LEDs Powerline
AGC Amplifier 802.3 MAC Controller for USB GPSI INT5130 Integrated Powerline MAC/PHY Transceiver
Coupler
USB
SPI
INT1000 Analog Conversion IC
Line Driver
Figure 28: USB to MII Application Diagram
LEDs Powerline
AGC Amplifier Embedded IC with integrated 802.3 MAC Controller GPSI INT5130 Integrated Powerline MAC/PHY Transceiver
Coupler
USB
SPI
INT1000 Analog Conversion IC
Line Driver
Figure 29: Embedded Application Diagram
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Electrical Specifications
Recommended Operating Conditions
Parameter Core Supply Voltage I/O Supply Voltage Operational Temperature Symbol VDD VCC TA Min 2.3 3.0 0 Typ 2.5 3.3 Max 2.7 3.6 +70 Unit V V C
Note: Recommended Operating Conditions are those values beyond which operation is not guaranteed.
DC Characteristics
Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW voltage Input Current Supply Current Supply Current Symbol VIH VIL VOH VOL II IDD ICC Test Conditions Min 2.0 0.8 IOH = -1mA IOL = 1mA 2.4 -15 465 25 0.4 15 Typ Max Unit V V V V A mA mA
Note: Any signal applied to the INT5130 clock pins, CLKIN and/or CLKOUT should not exceed 2.5 Volts.
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Physical Dimensions
.866 [22.00] .787 [20.00]
.020 [0.50] .004 [0.09]
.866 [22.00] .787 [20.00]
.009 [0.22]
.024 [0.60] .039 [1.00]
DETAIL "A"
123
SEE DETAIL "A" .059 [1.50]
PACKAGE OUTLINE LQFP 144 LEAD
DIMENSIONS NOMINAL BRACKETED DIMENSIONS ARE MM
.055 [1.40]
Figure 30: Physical Dimensions
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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Ordering Information
The INT5130 is available as part of the INT5130 Chipset, which includes both the INT5130 Integrated Powerline MAC/PHY Transceiver and the INT1000 Analog Conversion IC. Ordering information for the chipset is provided below. Catalog Part Number INT5130 CS Package Type INT5130: 144-pin LQFP INT1000: 64-pin LQFP Operating Range Commercial
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Intellon Corporation 5100 West Silver Springs Blvd. Ocala, FL 34482 (352) 237-7416 (352) 237-7616 (Fax) 2880 Lakeside Drive Suite #247 Santa Clara, CA 95054 (408) 567-1400 (408) 567-1401 www.intellon.com
(c)2001 Intellon Corporation. Intellon Corporation reserves the right to make changes to this document without notice. Intellon Corporation makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Intellon Corporation assumes no liability arising out of the application or use of any product or circuit. Intellon Corporation specifically disclaims any and all liability, including without limitation consequential or incidental damages. Intellon, PowerPacket, and No New Wires are registered trademarks of Intellon Corporation. HomePlug is a registered trademark of the HomePlug Powerline Alliance.
INTELLON CONFIDENTIAL
38
ADVANCE INFORMATION
014070108.1
Rev 8.1

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Price & Availability of INT5130

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